Recently, for driving a color plasma display panel (PDP) high voltage integrated circuits in which high voltage N-channel/P-channel MOS transistors are formed on a SOI substrate are frequently used.
The high voltage N-channel/P-channel transistor preferably has a high breakdown voltage in both on and off states. Now, two conventional examples of the high voltage P-channel MOS transistor will be described.
FIG. 3 shows a cross sectional view of the high voltage P-channel MOS transistor.
A semiconductor layer 3 is formed on a support substrate 1 through a buried oxide film 2. On the surface of the semiconductor layer 3, an N-type body region 4 and a P+-type drain region 9 are formed. On the surface of the N-type body region 4, a P+-type source region 8 and an N+-type diffused region 10 are formed. And a gate electrode 7 is formed on the edge of the N-type body region 4 via a gate oxide film 6.
In an off state, when a reverse bias is applied between the P+-type source region 8 and the P+-type drain region 9, a depletion region expands in a PN junction between the N-type body region 4 and a P-type drift region 5. The gate electrode 7 serves as a field plate, and an electric field increases in the surface of the P-type drift region 5 located below the end portion of the field plate 7. In order to improve an off-state breakdown voltage, the electric field must decrease.
Meanwhile, in an on-state, when the amount of drain current in the drift region 5 increases, a potential distribution is shifted toward the drain region by the Kirk effect. Therefore, the electric field increases in the edge of the P+-type drain region 9. When the diffusion depth of the P+-type drain region 9 is small, the electric field is concentrated to the P+-type drain region 9 and thus the breakdown voltage is reduced. In order to improve the breakdown voltage, an intermediate diffusion-layer (not shown) with a relatively high diffusion depth, is often inserted.
Next, the planar layout of the high voltage P-channel MOS transistor will be described.
In general, as a planar layout for improving the on-state voltage, there are known two conventional examples.
A first conventional example has a plane structure in which the P+-type drain region 9 is wholly surrounded by the N-type body region 4, as shown in FIG. 4. A portion of the P+-type source region is not formed on the surface of the annular N-type body region 4 surrounding the P+-type drain region 9. With this structure, a current density may be reduced in the edge of the drain region. So, it is possible to improve the on-state breakdown voltage.
A second conventional example has a plane structure in which the N-type body region 4 is wholly surrounded by the P+-type drain region 9 and the P-type drift region 5, as shown in FIG. 5. Since the circumferential length of the P+-type drain region 9 is large, the current density is reduced in the edge of the drain. Thereby the electric field can be suppressed, improving the on-state breakdown voltage.
FIG. 6 shows a relationship between drain voltage and drain current of the two conventional structures. In the first conventional example, the on-state breakdown voltage is a little more than 100 volts, whereas, in the second conventional example, the on-state breakdown voltage is a little less than 200 volts. The second conventional example has the layout in which the source body region is wholly surrounded by the drain region. Thus, it is possible to improve the on-state breakdown voltage.
However, the high voltage MOS transistor of the second conventional example has two problems as follows.
First, as shown in FIG. 6, a negative resistance region is observed in the drain voltage-current characteristics. It can be seen that the drain current decreases at the drain voltage more than 140 volts. Since the region due to heat generation is an unstable phenomenon that depends on an applied condition or thermal resistance, and thus must be reduced.
Second, an off-state breakdown voltage is slightly reduced compared with the high voltage MOS transistor of the first conventional example. In the high voltage MOS transistor of the second conventional example, the source body region is surrounded by the drain region in the end portion of the device. To this end, the curvature radius of the depletion region which extends from the body region to the drift region is smaller than that of the high voltage MOS transistor of the first conventional example and thus the electric field increases.
Accordingly, in the high voltage MOS transistor of the second conventional example, when the curvature radius of the end portion of the body region increases, the off-state breakdown voltage increases. However, the area of the device increases, which in turn increases the cost thereof.